1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device with multibank structure for the purpose of effectively activating and precharging word lines and bit lines.
The present application is based on Korean Application No. 30478/1995 which is incorporated herein by reference.
2. Description of the Related Art
In a central processing unit (CPU) and a memory, the more the number of banks of a dynamic random access memory (DRAM) increases, the more the number of word lines that can be kept in the active state increases. This may raise the page hit ratio of DRAM in case of cache miss thereby reducing the access time. In recent years, there has been a tendency to substitute a DRAM with increased banks in number for a static random access memory SRAM being used as a cache.
FIG. 1 depicts a conventional memory device with multibank structure.
As shown in FIG. 1, each one of four banks 0, 1, 2 and 3 consists of a memory cell array and a bit-line sense amplifier. Row address predecoders 10, 30, 60 and 80 are respectively provided to the banks 0, 1, 2 and 3. The row address predecoders 10, 30, 60 and 80 respectively have output lines 3, 5, 7 and 9. Column decoders 50, 51, 52 and 53 are assigned to each bank 0, 1, 2 and 3, too. Therefore, an increase in the number of the banks causes the size of a chip to be significantly increased, and it is hard to increase the banks in number.
FIG. 2 is a block diagram of a conventional semiconductor memory device with stacked multibank structure in which a plurality of banks have one row address predecoder and its output line in common.
Row address predecoders 10, 30, 60 and 80 and their respective output lines 3, 5, 7 and 9 are used in common for a bank group a (banks a1 to am), a bank group b (banks b1 to bm), a bank group c (banks c1 to cm), and a bank group d (banks d1 to dm). Regarding each word-line enabling/disabling operation and sensing operation of each bit-line sense amplifier, a bank activation in response to an active command of a preceding clock signal from an external system may be disabled by the following clock signal's precharge command given to another bank. Thus, the word-line precharging operation may be performed before the word line is disabled, or the corresponding bit-line sense amplifier may be actuated to perform the sensing operation before the word line is enabled.